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LHF32KZR
4
The access time is 70ns (t AVQV ) over the commercial
temperature range (0°C to +70°C) and V CC supply
voltage range of 4.75V-5.25V. At lower V CC voltages,
the access times are 80ns (4.5V-5.5V), 100ns (3.0V-
3.6V) and 120ns (2.7V-3.6V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I CCR current is 1 mA at 5V V CC .
When either BE 0 # or BE 1L #, BE 1H # and RP# pins are
at V CC , the I CC CMOS standby mode is enabled.
When the RP# pin is at GND, deep power-down
Bank1
mode is enabled which minimizes power
consumption and provides write protection during
reset. A reset time (t PHQV ) is required from RP#
switching high until outputs are valid. Likewise, the
device has a wake time (t PHEL ) from RP#-high until
writes to the CUI are recognized. With RP# at GND,
the WSM is reset and the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Bank0
Output
Buffer
DQ 0 -DQ 15
Query
Input
Buffer
ROM
I/O Logic
V CC
BYTE#
BE 0 #
BE 1H #
Idenrifier
Register
WE#
BE 0 #
BE 1L #
Status
Register
Data
Comparator
Multiplexer
Command
Register
OE#
RP#
WP#
A 0 -A 20
Input
Buffer
Y
Decoder
Y Gating
Write State
Machine
Program/Erase
Voltage Switch
STS
V PP
Address
Latch
X
Decoder
32
64KByte
V CC
GND
Blocks
Address
Counter
Figure 1. Block Diagram
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